1. Field of the Invention
The present invention relates to a scan path circuit constituted by a flip-flop having a scan function and a semiconductor integrated circuit comprising the scan path circuit.
2. Description of the Related Art
At present, semiconductor integrated circuits having circuit scales extending over 2000000 to 3000000 gates are designed. If so many logic circuits are to be completely tested, the amount of a test pattern and a time required for the test are enormously demanded. Therefore, a so-called test facilitating design has been carried out. In the test facilitating design, the policy of a failure test is decided in the stage of a circuit design and a test circuit is fabricated into a semiconductor integrated circuit to predict the cause of a failure and the circuit design is carried out such that a failure portion can easily be detected and diagnosed.
Examples of a method of carrying out such a failure test include a “scan path method”. In the scan path method, a sequential circuit is operated as a shift register to carry out a test. For example, in a conventional logic circuit shown in FIG. 14 which is constituted by D flip-flops 41 to 46 forming the sequential circuit and a combinational circuit 40, the flip-flops are connected to form a san path (a path for a test mode), thereby replacing each of the flip-flops with a scan flip-flop and operating the sequential circuit as a shift register. Then, data are scanned in and it is decided whether data scanned out are coincident with an expected value or not. Thus, the failure test is carried out.
The normal operation and test operation of the logic circuit shown in FIG. 14 will be described below.
First of all, during the normal operation, three sets of data are input from the D flip-flops (hereinafter referred to as “FFs”) 41 to 43 to the combinational circuit 40. Therefore, the combinational circuit 40 carries out a logical operation for the three sets of data, thereby outputting the three sets of data. The FFs 44 to 46 send the three sets of outputs to the outside.
During the test operation, the FFs 41 to 46 form a scan flip-flop, that is, a so-called scan path. The FFs 41 to 43 sequentially shift data input from an external test device synchronously with a predetermined clock. The combinational circuit 40 carries out a logical operation for the data given from the FFs 41 to 43 and outputs three sets of results of the operation. The FFs 44 to 46 sequentially shift the results of the operation which are given from the combinational circuit 40 and output the results to the outside. Since the output data include the results of the operation of the combinational circuit 40, it is decided whether the same results are coincident with an expected value or not. Thus, the failure of the combinational circuit 40 is decided.
However, in the case in which a shift register is constituted by a flip-flop as described above in the progress of the microfabrication process of a semiconductor integrated circuit, there is a possibility that a malfunction such as a hold error (a shift omission) might be caused, during a scan shift operation, by a clock skew, a variation in a device, a variation in a wiring or a cross talk. When the malfunction is generated, the reliability of a failure test is deteriorated. Consequently, there is a problem in that a yield is deteriorated. Such a problem can be solved by increasing a delay time in the scan shift operation. Consequently, an inverter and a latch for delaying a signal are provided between the flip-flops.
However, a problem is pointed out such that the inverter and the latch cannot cope with a variation in the delay characteristic of a device because they carry out a fixed delay. When the microfabrication process progresses, the variation in the device is increased. If the delay characteristic is not fixed but variable, the delay characteristic can be changed corresponding to each circuit. Consequently, it is possible to reliably prevent a malfunction such as a hold error. Accordingly, there has been desired a scan path circuit capable of flexibly coping with the variation in the delay characteristic of the device.
In a scan path circuit comprising an inverter and a latch, moreover, an extra area for mounting the inverter or the latch is required. Consequently, there is a problem in that the mounting area is increased. Accordingly, there has been desired a scan path circuit having a small mounting area which can prevent the malfunction of a scan shift operation to reliably carry out a failure test even if the inverter and the latch are not provided.